SDC
所有命令可以在以下网站查找
https://www.micro-ip.com/drchip.php?mode=2&cid=17
https://www.micro-ip.com/Synopsys(DC)/dictionary_24_8/create_generated_clock.html给出了create_generated_clock使用说明
转自http://docs.verilogtorouting.org/en/latest/vpr/file_formats/
这是Github上的一个工程 VPR (Versatile Place and Route) is an open source academic CAD tool designed for the exploration of new FPGA architectures and CAD algorithms, at the packing, placement and routing phases of the CAD flow [BR97b][LKJ+09]
The following subset of SDC syntax is supported by VPR:
create_clock
Creates a netlist or virtual clock.
assigns a desired period (in nanoseconds) and waveform to one or more clocks in the netlist (if the –name option is omitted) or to a single virtual clock (used to constrain input and outputs to a clock external to the design). Netlist clocks can be referred to using regular expressions, while the virtual clock name is taken as-is.
example Usage:
#Create a netlist clock
create_clock -period <float> <netlist clock list or regexes>
#Create a virtual clock
create_clock -period <float> -name <virtual clock name>
#Create a netlist clock with custom waveform/duty-cycle
create_clock -period <float> -waveform {rising_edge falling_edge} <netlist clock list or regexes>
Omitting the waveform creates a clock with a rising edge at 0 and a falling edge at the half period, and is equivalent to using -waveform {0 <period/2>}. Non-50% duty cycles are supported but behave no differently than 50% duty cycles, since falling edges are not used in analysis. If a virtual clock is assigned using a create_clock command, it must be referenced elsewhere in a set_input_delay or set_output_delay constraint.
create_clock
-period <float>
Specifies the clock period.
required: Yes
-waveform {<float> <float>}
Overrides the default clock waveform.
The first value indicates the time the clock rises, the second the time the clock falls.
Required: No
Default: 50% duty cycle (i.e. -waveform {0 <period/2>}).
-name <string>
Creates a virtual clock with the specified name.
Required: No
<netlist clock list or regexes>
Creates a netlist clock
Required: No
Note
One of -name or <netlist clock list or regexes> must be specified.
Warning
If a netlist clock is not specified with a create_clock command, paths to and from that clock domain will not be analysed.
set_clock_groups
Specifies the relationship between groups of clocks. May be used with netlist or virtual clocks in any combination.
Since VPR supports only the -exclusive option, a set_clock_groups constraint is equivalent to a set_false_path constraint (see below) between each clock in one group and each clock in another.
For example, the following sets of commands are equivalent:
#Do not analyze any timing paths between clk and clk2, or between
#clk and clk3
set_clock_groups -exclusive -group {clk} -group {clk2 clk3}
and
set_false_path -from [get_clocks {clk}] -to [get_clocks {clk2 clk3}]
set_false_path -from [get_clocks {clk2 clk3}] -to [get_clocks {clk}]
set_clock_groups
-exclusive
Indicates that paths between clock groups should not be analyzed.
Required: Yes
Note
VPR currently only supports exclusive clock groups
-group {<clock list or regexes>}
Specifies a group of clocks.
Note
At least 2 groups must be specified.
Required: Yes
set_false_path
Cuts timing paths unidirectionally from each clock in -from to each clock in –to. Otherwise equivalent to set_clock_groups.
Example Usage:
#Do not analyze paths launched from clk and captured by clk2 or clk3
set_false_path -from [get_clocks {clk}] -to [get_clocks {clk2 clk3}]
#Do not analyze paths launched from clk2 or clk3 and captured by clk
set_false_path -from [get_clocks {clk2 clk3}] -to [get_clocks {clk}]
Note
False paths are supported between entire clock domains, but not between inpidual registers.
set_false_path
-from [get_clocks <clock list or regexes>]
Specifies the source clock domain(s).
Required: No
Default: All clocks
-to [get_clocks <clock list or regexes>]
Specifies the sink clock domain(s).
Required: No
Default: All clocks
set_max_delay/set_min_delay
Overrides the default setup (max) or hold (min) timing constraint calculated using the information from create_clock with a user-specified delay.
Example Usage:
#Specify a maximum delay of 17 from input_clk to output_clk
set_max_delay 17 -from [get_clocks {input_clk}] -to [get_clocks {output_clk}]
#Specify a Minimum delay of 2 from input_clk to output_clk
set_min_delay 2 -from [get_clocks {input_clk}] -to [get_clocks {output_clk}]
Note
Max/Min delays are supported between entire clock domains, but not between inpidual netlist elements.
set_max_delay/set_min_delay
<delay>
The delay value to APPly.
Required: Yes
-from [get_clocks <clock list or regexes>]
Specifies the source clock domain(s).
Required: No
Default: All clocks
-to [get_clocks <clock list or regexes>]
Specifies the sink clock domain(s).
Required: No
Default: All clocks
set_multicycle_path
Sets how many clock cycles elapse between the launch and capture edges for setup and hold checks.
The default the setup mutlicycle value is 1 (i.e. the capture setup check is performed against the edge one cycle after the launch edge).
The default hold multicycle is one less than the setup multicycle path (e.g. the capture hold check occurs in the same cycle as the launch edge for the default setup multicycle).
Example Usage:
#Create a 4 cycle setup check, and 3 cycle hold check from clkA to clkB
set_multicycle_path -from [get_clocks {clkA}] -to [get_clocks {clkB}] 4
#Create a 3 cycle setup check from clk to clk2
# Note that this moves the default hold check to be 2 cycles
set_multicycle_path -setup -from [get_clocks {clk}] -to [get_clocks {clk2}] 3
#Create a 0 cycle hold check from clk to clk2
# Note that this moves the default hold check back to it's original
# position before the previous setup setup_multicycle_path was applied
set_multicycle_path -hold -from [get_clocks {clk}] -to [get_clocks {clk2}] 2
Note
Multicycles are supported between entire clock domains, but not between inpidual registers.
set_multicycle_path
-setup
Indicates that the multicycle-path applies to setup analysis.
Required: No
-hold
Indicates that the multicycle-path applies to hold analysis.
Required: No
-from [get_clocks <clock list or regexes>]
Specifies the source clock domain(s).
Required: No
Default: All clocks
-to [get_clocks <clock list or regexes>]
Specifies the sink clock domain(s).
Required: No
Default: All clocks
<path_multiplier>
The number of cycles that apply to the specified path(s).
Required: Yes
Note
If neither -setup nor -hold the setup multicycle is set to path_multiplier and the hold multicycle offset to 0.
set_input_delay/set_output_delay
Use set_input_delay if you want timing paths from input I/Os analyzed, and set_output_delay if you want timing paths to output I/Os analyzed.
Note
If these commands are not specified in your SDC, paths from and to I/Os will not be timing analyzed.
These commands constrain each I/O pad specified after get_ports to be timing-equivalent to a register clocked on the clock specified after -clock. This can be either a clock signal in your design or a virtual clock that does not exist in the design but which is used only to specify the timing of I/Os.
The specified delays are added to I/O timing paths and can be used to model board level delays.
For single-clock circuits, -clock can be wildcarded using * to refer to the single netlist clock, although this is not supported in standard SDC. This allows a single SDC command to constrain I/Os in all single-clock circuits.
Example Usage:
#Set a maximum input delay of 0.5 (relative to input_clk) on
#ports in1, in2 and in3
set_input_delay -clock input_clk -max 0.5 [get_ports {in1 in2 in3}]
#Set a minimum output delay of 1.0 (relative to output_clk) on
#all ports matching starting with 'out*'
set_output_delay -clock output_clk -min 1 [get_ports {out*}]
#Set both the maximum and minimum output delay to 0.3 for all I/Os
#in the design
set_output_delay -clock clk2 0.3 [get_ports {*}]
set_input_delay/set_output_delay
-clock <virtual or netlist clock>
Specifies the virtual or netlist clock the delay is relative to.
Required: Yes
-max
Specifies that the delay value should be treated as the maximum delay.
Required: No
-min
Specifies that the delay value should be treated as the minimum delay.
Required: No
<delay>
Specifies the delay value to be applied
Required: Yes
[get_ports {<I/O list or regexes>}]
Specifies the port names or port name regex.
Required: Yes
Note
If neither -min nor -max are specified the delay value is applied to both.
set_clock_uncertainty
Sets the clock uncertainty between clock domains. This is typically used to model uncertainty in the clock arrival times due to clock jitter.
Example Usage:
#Sets the clock uncertainty between all clock domain pairs to 0.025
set_clock_uncertainty 0.025
#Sets the clock uncertainty from 'clk' to all other clock domains to 0.05
set_clock_uncertainty -from [get_clocks {clk}] 0.05
#Sets the clock uncertainty from 'clk' to 'clk2' to 0.75
set_clock_uncertainty -from [get_clocks {clk}] -to [get_clocks {clk2}] 0.75
set_clock_uncertainty
-from [get_clocks <clock list or regexes>]
Specifies the source clock domain(s).
Required: No
Default: All clocks
-to [get_clocks <clock list or regexes>]
Specifies the sink clock domain(s).
Required: No
Default: All clocks
-setup
Specifies the clock uncertainty for setup analysis.
Required: No
-hold
Specifies the clock uncertainty for hold analysis.
Required: No
<uncertainty>
The clock uncertainty value between the from and to clocks.
Required: Yes
Note
If neither -setup nor -hold are specified the uncertainty value is applied to both.
set_clock_latency
Sets the latency of a clock. VPR automatically calculates on-chip clock network delay, and so only source latency is supported.
Source clock latency corresponds to the delay from the true clock source (e.g. off-chip clock generator) to the on-chip clock definition point.
#Sets the source clock latency of 'clk' to 1.0
set_clock_latency -source 1.0 [get_clocks {clk}]
set_clock_latency
-source
Specifies that the latency is the source latency.
Required: Yes
Specifies that the latency applies to early paths.
Required: No
-late
Specifies that the latency applies to late paths.
Required: No
<latency>
The clock’s latency.
Required: Yes
[get_clocks <clock list or regexes>]
Specifies the clock domain(s).
Required: Yes
Note
If neither -early nor -late are specified the latency value is applied to both.
set_disable_timing
Disables timing between a pair of connected pins in the netlist. This is typically used to manually break combinational loops.
#Disables the timing edge between the pins 'in[0]' and 'out[0]' on
#the netlist primitive named 'blk1'
set_disable_timing -from [get_pins {blk1.in[0]}] -to [get_pins {blk1.out[0]}]
set_disable_timing
-from [get_pins <pin list or regexes>]
Specifies the source netlist pins.
Required: Yes
-to [get_pins <pin list or regexes>]
Specifies the sink netlist pins.
Required: Yes
Special Characters
# (comment), \ (line continued), * (wildcard), {} (string escape)
# starts a comment – everything remaining on this line will be ignored.
\ at the end of a line indicates that a command wraps to the next line.
* is used in a get_clocks/get_ports command or at the end of create_clock to match all netlist clocks. Partial wildcarding (e.g. clk* to match clk and clk2) is also supported. As mentioned above, * can be used in set_input_delay and set_output delay to refer to the netlist clock for single-clock circuits only, although this is not supported in standard SDC.
{} escapes strings, e.g. {top^clk} matches a clock called top^clk, while top^clk without braces gives an ERROR because of the special ^ character.
SDC Examples
The following are sample SDC files for common non-default cases (assuming netlist clock domains clk and clk2).
A
Cut I/Os and analyse only register-to-register paths, including paths between clock domains; optimize to run as fast as possible.
create_clock -period 0 *
B
Same as A, but with paths between clock domains cut. Separate target frequencies are specified.
create_clock -period 2 clk
create_clock -period 3 clk2
set_clock_groups -exclusive -group {clk} -group {clk2}
C
Same as B, but with paths to and from I/Os now analyzed. This is the same as the multi-clock default, but with custom period constraints.
create_clock -period 2 clk
create_clock -period 3 clk2
create_clock -period 3.5 -name virtual_io_clock
set_clock_groups -exclusive -group {clk} -group {clk2}
set_input_delay -clock virtual_io_clock -max 0 [get_ports {*}]
set_output_delay -clock virtual_io_clock -max 0 [get_ports {*}]
D
Changing the phase between clocks, and accounting for delay through I/Os with set_input/output delay constraints.
#Custom waveform rising edge at 1.25, falling at 2.75
create_clock -period 3 -waveform {1.25 2.75} clk
create_clock -period 2 clk2
create_clock -period 2.5 -name virtual_io_clock
set_input_delay -clock virtual_io_clock -max 1 [get_ports {*}]
set_output_delay -clock virtual_io_clock -max 0.5 [get_ports {*}]
E
Sample using many supported SDC commands. Inputs and outputs are constrained on separate virtual clocks.
create_clock -period 3 -waveform {1.25 2.75} clk
create_clock -period 2 clk2
create_clock -period 1 -name input_clk
create_clock -period 0 -name output_clk
set_clock_groups -exclusive -group input_clk -group clk2
set_false_path -from [get_clocks {clk}] -to [get_clocks {output_clk}]
set_max_delay 17 -from [get_clocks {input_clk}] -to [get_clocks {output_clk}]
set_multicycle_path -setup -from [get_clocks {clk}] -to [get_clocks {clk2}] 3
set_input_delay -clock input_clk -max 0.5 [get_ports {in1 in2 in3}]
set_output_delay -clock output_clk -max 1 [get_ports {out*}]
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